1. Introduction 1.1 Purpose This purpose of this document is to describe the CPU board on the Neutral Gas Ion Mass Spectrometer (NGIMS) on the Comet Nucleus Tour (CONTOUR) spacecraft. This document includes a top level description of the CPU board, its memory map, and schematics of the CPU board. The CPU board is used to receive and process spacecraft communications and as a primary controller for the following subsystems: 1. Program Memory (PROM & SRAM) 2. Auxillary memory (SRAM & EEPROM) 3. 1553 interface (DDC BU-61582) 4. Microsequencer board 5. UART and LED Board 6. Watchdog timer 7. Configuration registers 8. Wait state generator 9. Other IO locations 1.2 Scope This document describes the NGIMS CPU board. Details of the software that controls the board are contained in other documents (see reference section). 1.3 Acronyms CPU Central Processing Unit DDC Data Device Corporation EEPROM Electrically erasable programmable read-only memory INMS Ion Neutral Mass Spectrometer IO Input Output LED Light emitting Device NGIMS Neutral Gas Chromatograph Mass Spectrometer PROM Programmable read-only memory SRAM Static Random access memory UART Universal Asynchronous Receiver Transmitter 1.4 References (1) ACE/Mini-ACE Series BC/RT/MT Advanced Communication Engine Intergrated 1553 Terminal BU-61580/BU-61585 User's Guide (2) Harris Radiation Hardened Product Databook (3) MA31750 MIL-STD-1750 Microproccessor Datasheet (4) MIL-STD-1750 (5) MIL_STD_1553 A tutorial Alan M. Dunn (6) CONTOUR 1553 Bus Specification Version 0.0 Robyn LeGrys 1.5 Nomenclature All references to address and data bits follows the little Endian format that is: The low order bit 2. Overview The CPU board was based on a rework of INMS's CPU, Memory and 1553 BIU boards. These cards were integrated onto a unified design on a single board by taking advantage of the higher density memory RAM and PROMs that are now available. In addition, communications with the spacecraft's C & DH 1553 bus is handled by the DDC 1553 BU-61582 chip instead of the JPL-provided BIU interface board on INMS. The NGIMS CPU board consists of: Marconi 31750 CPU Running at 8 MHz 64Kwords One-Time-Programmable (OTP) EPROM - 0 wait states 64Kwords SRAM- 0 wait states 64Kwords IO RAM - 0 wait states 128Kwords paged EEPROM - 0 wait states 1553 interface using the DDC 61582 hybrid (with 16Kwords on chip memory) - variable wait state dependent on the DDC 61582 READY signal. All communications with the spacecraft will be via its 1553 interface. Details of the CONTOUR 1553 Bus Specification can be found in the references specified above. 3. Memory and I/O Space Organization The MA31750 is a Harvard architecture CPU. It has 16 Address Bits plus 4 address state bits and 16 data bits. The memory space is addressed when the M/IO bit is set (= 1). An M/IO status line allows memory (M/IO bit = 1) and IO (M/IO bit = 0) operation. The IO space is further split into half because the type of IO (whether R or WR) operation depends on the destination of the IO operation. An XIO access to a location above 8000h (A15 = 1) causes the following signals M/IO = 0 R/WR = 0 and WR = 0 to be generated by the CPU. Thus a total of 64 KW of memory space, 32K I/O Write and 32KW IO Read space are addressable using the CPU. In order to address more than that, memory mapped IO schemes were implemented. Below is a description of the memory space and IO space in the NGIMS. Memory Space: 64 KW I/O Space: Input 32KW, Output 32KW 64KW Memory Space 0ffffh PROM RAM 00000h PROM and RAM space are overlaid on top of each other. The SUREN signal is used to page between the two spaces. The following instructions modifies the polarity of the SUREN pin. XIO Rn, ESUR ; enable startup rom, pulls SUREN low XIO Rn, DSUR ; disable startup rom, pulls SUREN high 32KW I/O Space bit 15 = 1 IN bit 15 = 0 OUT To expand the available I/O space, the MA31750's AS[0:3] are used as the high nibble of the address bus to extend it to 20 bits. The value of the AS bits is reflected by the value of the Status Word register within the CPU. The following 1750 instructions are used to change the AS bits of the Status Word register. XIO R0, RSW ; R0 contains the current status word ANDM R0, 0FFF0H ; Clear least significant nibble of the SW ORIM R0, IO_PAGEn ; Put desired the IO page number into R0 XIO R0, WSW ; Write R0 to the status word register Status Word Register Format 15...12 11...8 7...4 3...0 CS Resvd PS AS The resulting 20 address bits can be used to access higher I/O space expanding it to accomodate a theoretical total of 16*32KW input or output I/O space. But in accordance to the Sixteen-Bit Computer Instruction Set Architecture MIL-STD-1750A, Section 4.8.3, Table IX, certain I/O areas are keep out areas. We placed our regular I/O channel groups between address locations 6000h - 61ffh / e000h - e1ffh and vary our spare I/O channel groups between ?6000h - ?7fffh / ?e000h - ?e7fffh. We did not decode addresses 10000h - 3ffffh. This is illustrated below: 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 i/o 1 1 0 0 0 0 ? ? ? ? ? ? ? ? ? 0 1 0 0 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 0 1 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 1 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0 0 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0 1 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 1 0 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 1 1 i/o 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? Regular I/O 06000 - 061ffh I/O Output Space 0e000 - 0e1ffh I/O Input Space spare I/O 46000 - 47fffh I/O Output Space - Page 1 4e000 - 4ffffh I/O Input Space - Page 1 56000 - 57fffh I/O Output Space - Page 2 5e000 - 5ffffh I/O Input Space - Page 2 66000 - 67fffh I/O Output Space - Page 3 6e000 - 6ffffh I/O Input Space - Page 3 76000 - 77fffh I/O Output Space - Page 4 7e000 - 77fffh I/O Input Space - Page 4 86000 - 87fffh I/O Output Space - Page 5 8e000 - 8ffffh I/O Input Space - Page 5 96000 - 97fffh I/O Output Space - Page 6 96000 - 9ffffh I/O Input Space - Page 6 a6000 - a7fffh I/O Output Space - Page 7 ae000 - affffh I/O Input Space - Page 7 b6000 - b7fffh I/O Output Space - Page 8 be000 - bffffh I/O Input Space - Page 8 Since the AS bits were used only for I/O space decode, memory space accesses are not affected when the AS bits are changed. This allows the software to continue executing from RAM while paging from one I/O space to the next. Memory map of the NGIMS board: 00000-0ffffh (r) PROM 64KWords 00000-0ffffh (r) RAM 64KWords I/O map: bit 0: lsb, bit 15: msb 08410 (r) configuration register 15: MMU Select 0 (1) 14: No BPU in system (0) 13: Console mode disabled (0) 12: MMU Select 1 (1) 11: Interrupt Sensitivity (0 = edge) 10: MMU Select 2 (1) 9: Parity sense; (0 = even) 8: BIT; (1=BIT on power up) 7: SUREN (1 = enabled) 6: DMA (0 = none) 5: unused (pulled high) 4: unused (pulled high) 3: unused (pulled low) 2: control C bit (toggles) 1: TGO\_STAT; 0 = TGO didn't occur; 1 = TGO occured 0: SUREN_stat; 0 = in PROM mode; 1 = in RAM mode Reset status ports 6040h (r/w) any read or write clears TGO status bit Microsequencer ports 6080h (w) 2 bytes Write Cmd Word to useq cmd FIFOs e080h (r) 2 bytes Read data from useq data FIFO 6081h (w) Reset useq cmd FIFOs e081h (r) word read useq status 6082h (w) Enable uSeq 6083h (w) Start uSeq Clock uSeq requires a 4MHz 50% duty cycle clock. MicroSequencer Status bits e0a0h (r) 1 word read status word from Microsequencer Spares: 06060h Digital Control Signals: 060c0h (w) 16 bits 060e0h (w) 16 bits UART port* 6100h (w) byte data output port 6101h (w) byte control port e100h (r) byte data input port e101h (r) byte status port 7-segment displays and LED ports* 06120h (w) word 7 segment test LEDs 06121h (w) word 7 segment test LEDs 06140h (w) word 7 segment test LEDs 06141h (w) word 7 segment test LEDs 06160h (w) word 7 segment test LEDs 06161h (w) word 7 segment test LEDs 06180h (w) word 7 segment test LEDs 06181h (w) word 7 segment test LEDs 061a0h (w) word 7 segment test LEDs 061a1h (w) word 7 segment test LEDs 061c0h (w) word 7 segment test LEDs 061c1h (w) word Individual test LEDs 061e0h (w) word Individual test LEDs 061e1h (w) word Individual test LEDs 1553 Memory 16000-17fffh (w) 1553 MEM 8Kwords 26000-27fffh (w) 1553 MEM 8KWords 1e000-1ffffh (r) 1553 MEM 8KWords 2e000-2ffffh (r) 1553 MEM 8KWords 1553 interface (registers): 06000-0601f (w) 1553 REG 32 words 0e000-0e01f (r) 1553 REG 32 words Page registers: 06030h - 0603fh 06030h (w) Write to data bit 0 & 1 to access high 64KW bank of EEPROM D[0..1] Position Area affected 00 1st 64K bytes chip 0 bank 0 01 2nd 64K bytes chip 0 bank 1 10 3rd 64K bytes chip 1 bank 0 11 4th 64K bytes chip 1 bank 1 06032h (w) Write to data bit 0 to access 32KW bank of XRAM D[0] Position Area affected 0 1st 32KW RAM chip, 3rd 32KW bank 1 2nd 32KW RAM Chip 4th 32KW bank 0e030h (r) Reads status of page registers, EEPROM ready signal bit position 0 0 = EEPROM 0 selected, 1 = EEPROM 1 selected 1 0 = low 64Kbyte selected, 1 = high 64 Kbyte selected 2 3 4 5 6 7 0 = low 32 Kword IORAM seleected, 1 = High 32 Kword IORAM selected 8 0 = EEPROM chip 0 ready, 1 = not ready 9 0 = EEPROM chip 1 ready, 1 = not ready 0e031h Data bit 2: (0 = low bank; 1 = High bank) of EEPROM selected Data bit 8: low byte status; 1 not ready, 0 = ready Data bit 9: High Byte status; 1 not ready, 0 = ready EEPROM IO ( 8 pages X 8 Kbytes = 64 Kbytes per bank) 46000-47fffh (w) EEPROM MEM 8KBytes 56000-57fffh (w) EEPROM MEM 8KBytes 66000-67fffh (w) EEPROM MEM 8KBytes 76000-77fffh (w) EEPROM MEM 8KBytes 86000-87fffh (w) EEPROM MEM 8KBytes 96000-97fffh (w) EEPROM MEM 8KBytes a6000-a7fffh (w) EEPROM MEM 8KBytes b6000-b7fffh (w) EEPROM MEM 8KBytes 4e000-4ffffh (r) EEPROM MEM 8KBytes 5e000-5ffffh (r) EEPROM MEM 8KBytes 6e000-6ffffh (r) EEPROM MEM 8KBytes 7e000-7ffffh (r) EEPROM MEM 8KBytes 8e000-8ffffh (r) EEPROM MEM 8KBytes 9e000-9ffffh (r) EEPROM MEM 8KBytes ae000-affffh (r) EEPROM MEM 8KBytes be000-bffffh (r) EEPROM MEM 8KBytes Extra RAM (Note: 2 pages of XRAM exists, selected by a write to IO location 6032) NB: bit 0 = lsb c6000-c7fffh (w) IORAM 8KWords d6000-d7fffh (w) IORAM 8KWords e6000-effffh (w) IORAM 8KWords f6000-b6fffh (w) IORAM 8Kwords ce000-cffffh (r) IORAM 8KWords de000-dffffh (r) IORAM 8KWords ee000-effffh (r) IORAM 8KWords fe000-fffffh (r) IORAM 8KWords Interrupts INT02N dtstarti 1553cmdi\ interrupt (24,25) INT08N uSeqI uSeq Interrupt (30,31) INT10N spare spare (34,35) INT11N rti 1553int\ interrupt (36,37) INT13N spare (3A,3B) * Will not be part of the Flight Boards. Used for Debug Purposes only. Revised 10/26/99 Florence Tan 1/14/00 Florence Tan - corrected LED assignment (individual vs 7-segment),Clarified page register notes on EEPROM and XRAM 6/1/2000 Ft - updated page register assignments. EEPROMs now addressed as bytes instead of words. Also, new data bit assignments to 0E030h.